An MOS (Metal-Oxide-Semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
There are generally two types of MOS field-effect transistors (FETs), namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated within a semiconductor substrate, typically monocrystalline silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of holes or electrons. This invention is specific to NMOS transistors.
FIG. 1 illustrates a semiconductor wafer fragment 10 which depicts an NMOS field-effect transistor. Such is comprised of a bulk lightly doped p-type substrate 12 having a gate terminal 14, as well as source and drain terminals 16 and 18, respectively. Gate terminal 14 is comprised of a conductive polysilicon layer 20 and overlying higher conducting silicide layer 21. A gate oxide layer 22 is positioned intermediate polysilicon layer 20 and bulk substrate 12. Gate terminal 14 is encapsulated by electrically insulating sidewall spacers 23 and a cap 24. The bulk substrate region between source 16 and drain 18 constitutes a channel of some defined length. The source and drain regions are heavily doped with n-type material. Application of an input voltage to gate terminal 14 sets up a transverse electric field in the channel region. By varying this transverse electric field, it is possible to modulate the longitudinal conductance of the channel region.
As MOS channel lengths (i.e., gate widths) got smaller than about 3 microns, so-called short-channel effects began to become increasingly significant. As a result, device design and consequently process technology had to be modified to take these effects into account so that optimum device performance could continue to be obtained. For example as device dimensions are reduced and the supply voltage remains constant, the lateral electric field generated in MOS devices increases. If the field becomes strong enough, it can give rise to so-called hot-carrier effects in MOS devices. This becomes a significant problem in NMOS devices with channel lengths smaller than 1.5 microns. Hot-carrier effects cause unacceptable performance degradation in NMOS devices built with conventional drain structures if their channel lengths are less than 2 microns.
A preferred method of overcoming this problem is to provide the illustrated lightly doped drain regions 25 relative to the channel region in advance of the source and drain regions. The LDD regions are provided to be lighter doped (i.e., less concentration) than the source and drain regions. This facilitates sharing of the voltage drop by the drain and the channel, as opposed to the stark voltage drop at the channel occurring in non-LDD NMOS devices. The LDD regions absorb some of the voltage drop potential into the drain, thus effectively eliminating hot carrier effects. As a result, the stability of the device is greatly increased.
However, further shrinking of the NMOSFET width (i.e., shorter channel length) makes the LDD region of a conventional NMOS LDD transistor less effective because of reduced LDD length. It would be desirable to develop alternate methods and structures which accommodate reduced intrinsic channel length the result of tighter integration densities.